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3.8 Audio Driver

The audio driver receives and transmits samples from/to the decoupler or mixer

core over an XC channel. It then drives several in and out I2S channels. If the

ﬁrmware is conﬁgured with the CODEC as slave, it will also drive the word and bit

clocks in this core as well. The word clocks, bit clocks and data are all derived

from the incoming master clock (the output of the external clocking chip). The

audio driver is implemented in the ﬁle audio.xc.

The audio driver captures and plays audio data over I2S. It also forwards on relevant

audio data to the S/PDIF transmit core.

The audio core must be connected to a CODEC that supports I2S (other modes

such as “left justiﬁed” can be supported with ﬁrmware changes). In slave mode,

the XS1 device acts as the master generating the Bit Clock (BCLK) and Left-Right

Clock (LRCLK, also called Word Clock) signals. Although the reference designs use

the Cirrus CS4270/CS42448, any CODEC that supports I2S and can be used.

Figure 10 shows the signals used to communicate audio between the XS1 device

and the CODEC.

Signal Description

LRCLK The word clock, transition at the start of a sample

BCLK The bit clock, clocks data in and out

SDIN Sample data in (from CODEC to XS1-L)

SDOUT Sample data out (from XS1-L to CODEC)

MCLK The master clock running the CODEC

Figure 10:

CODEC

Signals

The bit clock controls the rate at which data is transmitted to and from the CODEC.

In the case where the XS1 device is the master, it divides the MCLK to generate

the required signals for both BCLK and LRCLK, with BCLK then being used to clock

data in (SDIN) and data out (SDOUT) of the CODEC.

Figure 11 shows some example clock frequencies and divides for diﬀerent sample

rates (note that this reﬂects the single tile L-Series reference board conﬁguration):

Sample Rate (kHz) MCLK (MHz) BCLK (MHz) Divide

44.1 11.2896 2.819 4

88.2 11.2896 5.638 2

176.4 11.2896 11.2896 1

48 24.576 3.072 8

96 24.576 6.144 4

192 24.576 12.288 2

Figure 11:

Clock Divides

used in single

tile L-Series

Ref Design

The master clock must be supplied by an external source e.g. clock generator

chip, ﬁxed oscillators, PLL etc to generate the two frequencies to support 44.1kHz

and 48kHz audio frequencies (e.g. 11.2896/22.5792MHz and 12.288/24.576MHz

REV 6.1

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