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outuint Sample frequency (Hz)

outuint Master clock frequency (Hz)

outuint Left sample

outuint Right sample

outuint Left sample

outuint Right sample

...

outct Terminate

Figure 17:

S/PDIF

Component

Protocol

Bits

0:3 Preamble Correct B M W order, starting at sample 0

4:27 Audio sample Top 24 bits of given word

28 Validity bit Always 0

29 Subcode data (user bits) Unused, set to 0

30 Channel status See below

31 Parity Correct parity across bits 4:30

Figure 18:

S/PDIF

Stream

Structure

Frequency (kHz) n

44.1 0

48 2

88.2 8

96 A

176.4 C

192 E

Figure 19:

Channel

Status Bits

3.11 S/PDIF Receive

XS1 devices can support S/PDIF receive up to 192kHz.

The S/PDIF receiver module uses a clockblock and a buﬀered one-bit port. The

clock-block is divided of a 100 MHz reference clock. The one bit port is buﬀered

to 4-bits.

The receiver outputs audio samples over a streaming channel end where data can

be input using the built-in input operator.

The S/PDIF receive function never returns. The 32-bit value from the channel input

comprises:

The tag has one of three values:

See S/PDIF speciﬁcation for further details on format, user bits etc.

REV 6.1

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